Method of manufacturing semiconductor device, and semiconductor device

ABSTRACT

A method of manufacturing a semiconductor device includes: the first step of forming a gate electrode over a silicon substrate, with a gate insulating film; and the second step of digging down a surface layer of the silicon substrate by etching conducted with the gate electrode as a mask. The method of manufacturing the semiconductor device further includes the third step of epitaxially growing, on the surface of the dug-down portion of the silicon substrate, a mixed crystal layer including silicon and atoms different in lattice constant from silicon so that the mixed crystal layer contains an impurity with such a concentration gradient that the impurity concentration increases along the direction from the silicon substrate side toward the surface of the mixed crystal layer.

CROSS REFERENCES TO RELATED APPLICATIONS

The application is a Reissue Application of Ser. No. 11,739,792, filedApr. 25, 2007, now U.S. Pat. No. 7,510,925, issued Mar. 31, 2009. Thepresent invention contains subject matter related to Japan PatentApplication JP 2006-121605 filed with the Japan Patent Office on Apr.26, 2006, the entire contents of which being incorporated herein byreference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of manufacturing asemiconductor device and the semiconductor device, particularly to a MOS(Metal Oxide Semiconductor) type field effect transistor.

2. Description of the Related Art

In recent years, for the purpose of enhancing the performance oftransistors, impressing of a stress on a channel region so as toincrease the drain current has been investigated. Examples of the stressimpressing method include a method in which a highly stressed film isformed after the formation of a gate electrode so as to impress a stresson a channel region, and a process in which the source/drain regions ofa P-channel MOS type field effect transistor (PMOSFET) are etched, and asilicon-germanium (SiGe) layer is epitaxially grown in the etched areasto exert a stress on a channel region.

The application of a stress to the channel region is more effective asthe SiGe layer is closer to the channel region and as the volume of theSiGe layer is greater. Furthermore, while the source/drain regions areformed generally by ion implantation, addition of an impurity such asboron simultaneously with the epitaxial growth of the SiGe layer hasalso been investigated as a method of forming the source/drain regionsof a PMOSFET (refer, for example, to JP-A-2002-530864, refer,particularly, to FIG. 4 and paragraph No. 0030).

Here, the above-mentioned method of manufacturing a PMOSFET will bedescribed referring to FIGS. 4A to 4C 3A to 3C. First, as shown in FIG.4A 3A, device isolation regions (omitted in the figure) are formed onthe face side of a silicon substrate 11. Next, a gate electrode 13 isformed over the silicon substrate 11, with a gate insulating film 12therebetween, and an offset insulating film 14 including a siliconnitride film is formed on the gate electrode 13. Subsequently, a siliconnitride film is formed over the silicon substrate 11 in the state ofcovering the gate insulating film 12, the gate electrode 13 and theoffset insulating film 14, and the silicon nitride film is etched backby a dry etching method, whereby side walls 15 are formed on bothlateral sides of the gate insulating film 12, the gate electrode 13 andthe offset insulating film 14.

Next, as shown in FIG. 4B 3B, the so-called recess etching, i.e.,digging down the silicon substrate 11 by etching with the offsetinsulating film 14 and the side walls 15 as a mask, is conducted to formrecess regions 16. Thereafter, a natural oxide film over the surface ofthe silicon substrate 11 is removed by a cleaning treatment usingdiluted hydrofluoric acid.

Subsequently, as shown in FIG. 4C 3C, a silicon-germanium (SiGe) layer17 containing a p-type impurity such as boron is epitaxially grown inthe recess regions 16, i.e., on the surfaces of the dug-down portions ofthe silicon substrate 11. The SiGe layer 17 forms the source/drainregions, and the region, beneath the gate electrode 13 and locatedbetween the source/drain regions, of the silicon substrate 11constitutes the channel region 18. The application of a stress to thechannel region 18 by the SiGe layer 17 causes a straining (distortion)of the channel region 18, resulting in the formation of a PMOSFET havinga sufficient carrier mobility.

SUMMARY OF THE INVENTION

However, the above-mentioned method of manufacturing a semiconductordevice has the following problem. As shown in FIG. 5 4, the efficiencyof impressing the stress by the SiGe layer 17 is higher as the SiGelayer 17 is closer to the region beneath the gate electrode 13 whichserves as the channel region 18. However, since the impurity such asboron is added to the SiGe layer 17, the impurity in the SiGe layer 17would be diffused (diffused regions A) by the heat treating or heatingsteps carried out in the subsequent steps. This diffusion would causethe short channel effect. In order to prevent such a situation, it maybe contemplated to enlarge the distance between the region beneath thegate electrode 13 and the SiGe layer 17 to which boron is added. In thatcase, however, the stress exerted on the channel region 18 is weakened,so that a sufficient carrier mobility may not be obtained.

Thus, there is a need for a method of manufacturing a semiconductordevice, and the semiconductor device, with which the short channeleffect can be prevented and a sufficient carrier mobility can beobtained.

According, to an embodiment of the present invention, there is provideda method of manufacturing a semiconductor device, including: the firststep of forming a gate electrode, the second step of digging down asurface layer, and the third step of epitaxially growing. The first stepis configured to form a gate electrode, over a silicon substrate, with agate insulating film. The second step is configured to dig down asurface layer of the silicon substrate by etching conducted with thegate electrode as a mask. The third step is configured to epitaxiallygrow, on the surface of the dug-down portion of the silicon substrate, amixed crystal layer including silicon and atoms different in latticeconstant from silicon so that the mixed crystal layer contains animpurity with such a concentration gradient that the impurityconcentration increases along the direction from the silicon substrateside toward the surface of the mixed crystal layer.

According to the method of manufacturing a semiconductor device asjust-mentioned, on the surface of the dug-down portion of the siliconsubstrate, the mixed crystal layer is epitaxially grown so as to containthe impurity with such a concentration gradient that the impurityconcentration increases along the direction from the silicon substrateside toward the surface. Therefore, the mixed crystal layer in thevicinity of the channel region, beneath the gate electrode, of thesilicon substrate contains the impurity in a lower concentration ascompared with that on the surface side. This ensures that the diffusionof the impurity from the mixed crystal layer due to a heat treatment isrestrained, and the short channel effect is prevented from beinggenerated. In addition, since it is unnecessary to enlarge the distancebetween the region beneath the gate electrode and the mixed crystallayer, a sufficient carrier mobility can be obtained.

According to another embodiment of the present invention, there isprovided a semiconductor device including: a gate electrode providedover a silicon substrate, with a gate insulating film; and a mixedcrystal layer including silicon and atoms different in lattice constantfrom silicon, in regions where the silicon substrate is dug down on bothlateral sides of the gate electrode. The mixed crystal layer containsthe impurity with such a concentration gradient that the impurityconcentration increases along the direction from the silicon substrateside toward the surface.

According to the semiconductor device as just-mentioned, the mixedcrystal layer containing the impurity with a concentration gradient suchthat the impurity concentration increases along the direction from thesilicon substrate side toward the surface. Therefore, the mixed crystallayer in the vicinity of the channel region, beneath the gate electrode,of the silicon substrate contains the impurity in a lower concentrationas compared with that on the surface side. This ensures that thediffusion of the impurity from the mixed crystal layer due to a heattreatment is restrained, and the short channel effect is prevented frombeing generated. In addition, since it is unnecessary to enlarge thedistance between the region beneath the gate electrode and the mixedcrystal layer, a sufficient carrier mobility can be obtained.

As has been above-mentioned, according to the method of manufacturing asemiconductor device and the semiconductor device which pertain to thepresent invention, the short channel effect can be prevented from beinggenerated, and a sufficient carrier mobility can be obtained, so thattransistor characteristics can be enhanced.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1G are manufacturing step sectional diagrams forillustrating a first embodiment of the method of manufacturing asemiconductor device pertaining to the present invention;

FIGS. 2A to 2C are manufacturing step sectional diagrams forillustrating a second embodiment of the method of manufacturing asemiconductor device pertaining to the present invention;

FIGS. 3A to 3C are manufacturing step sectional diagrams forillustrating a method of manufacturing a semiconductor device accordingto the related art; and

FIG. 4 is a sectional diagram for illustrating a problem in the methodof manufacturing a semiconductor device according to the related art.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Now, some embodiments of the present invention will be described below,based on the drawings. In each of the embodiments, the configuration ofa semiconductor device will be described in the order of manufacturingsteps.

First Embodiment

An embodiment of the method of manufacturing a semiconductor devicepertaining to the present invention will be described below, taking themethod of manufacturing a PMOSFET as an example and referring to themanufacturing step sectional diagrams in FIGS. 1A to 2G. Incidentally,in the following description, the same configurations as those describedin the background of the invention above will be denoted by the samesymbols as used above.

First, as shown in FIG. 1A, a silicon substrate 11 composed of singlecrystal silicon is prepared, and device isolation regions are formed onthe face side thereof. In this case, for example, device isolationregions of the STI (shallow trench isolation) structure are formed, inwhich trenches are formed on the face side of the silicon substrate 11,and an insulating film composed of a silicon oxide film, for example, isburied in the trenches.

Next, on the silicon substrate 11 in each area isolated by the deviceisolation regions, a gate electrode 13 composed of polysilicon, forexample, is patterned, with a gate insulating film 12 composed of asilicon oxynitride film, for example, therebetween. In this case, inorder that an offset insulating film 14 composed of a silicon nitridefilm, for example, is provided on the gate electrode 13, films ofmaterials for constituting the gate insulating films 12, the gateelectrodes 13 and the offset insulating films 14 are layered in astacked state, and the stack of films is subjected to pattern etching.

Here, the material constituting the gate insulating film 12 is notlimited to the silicon oxynitride film, and may be a silicon oxide filmor a metallic oxide film containing hafnium or aluminum. In addition,the gate electrode 13 is not limited to polysilicon, and may contain ametallic material.

Next, as shown in FIG. 1B, for example, a silicon nitride film 15′ isformed over the silicon substrate 11 in the state of covering the gateinsulating films 12, the gate electrodes 13, and the offset insulatingfilms 14. Subsequently, as shown in FIG. 1C, the silicon nitride film15′ (see FIG. 1B) is etched back by a dry etching method, for example,whereby insulating side walls 15 are formed on side walls of the gateinsulating film 12, the gate electrode 13, and the offset insulatingfilm 14. While the side walls 15 are described to be composed, forexample, of silicon nitride film here, the side walls 15 may be composedof other film than the silicon nitride film, and may be configured ofsilicon oxide film or a stacked structure of these films.

Next, as shown in FIG. 1D, recess etching which includes in digging downthe surface of the silicon substrate 11 is conducted. In this case, therecess etching of digging down the surface layer of the siliconsubstrate 11 is realized by etching which is conducted with use of theoffset insulating film 14 on the gate electrode 13 and the side walls 15as a mask, whereby recess regions 16 about 80 nm deep are formed. In therecess etching, an isotropic etching is conducted, whereby the recessregion 16 can be broadened even to the lower side of the side walls 15.Thereafter, a cleaning treatment is conducted using diluted hydrofluoricacid, whereby a natural oxide film on the surface of the siliconsubstrate 11 is removed. Incidentally, while an example in which therecess etching is conducted in the condition where the side walls 15have been provided is described here, the present invention isapplicable also to the case where the recess etching is carried outwithout the side walls 15 provided in advance.

Subsequently, a mixed crystal layer containing silicon and atomsdifferent in lattice constant from silicon is epitaxially grown, in animpurity-containing state, on the surfaces of the recess regions 16,i.e., on the surfaces of the dug-down portions of the silicon substrate11. Here, an SiGe layer (mixed crystal layer) composed of silicon (Si)and atoms (Ge) larger than silicon in lattice constant and containing,for example, boron as an impurity is epitaxially grown, in view of thePMOSFET intended to be produced.

In this case, as a characteristic feature of the present invention, onthe surfaces of the dug-down portions of the silicon substrate 11, theSiGe layer is epitaxially grown so as to contain boron with such aconcentration gradient that the boron concentration therein increasesalong the direction from the side of the silicon substrate 11 toward thesurface thereof. Here, the SiGe layer is composed of a first SiGe layer(first layer), a second SiGe layer (second layer) and a third SiGe layer(third layer) which are sequentially layered in a stacked state.

Specifically, as shown in FIG. 1E, on the surfaces of the dug-downportions of the silicon substrate 11, i.e., on the surfaces of therecess regions 16, the first SiGe layer 21a is formed so as to containboron in the lowest concentration among the three SiGe layers. Here, thefirst SiGe layer 21a is epitaxially grown in a film thickness of one to30 nm so as to obtain a boron concentration of 1×10¹⁸ to 1×10¹⁹ cm⁻³.

As for the film forming conditions for the first SiGe layer 21a,dichlorosilane (DCS), germanium hydride (GeH₄) diluted with hydrogen(H₂) to 1.5 vol %, hydrogen chloride (HCl), and diborane (B₂H₆) dilutedwith hydrogen (H₂) to 100 ppm are used as film-forming gases, at gasflow rates of DCS/GeH₄/HCl/B₂H₆=ten to 100/ten to 100/ten to 100/one to50 (ml/min), a treating temperature of 650 to 750° C., and a treatingpressure of 1.3 to 13.3 kPa. It is to be noted that the gas flow ratesare volume flow rates in the normal state, here and hereinafter.

Here, the first SiGe layer 21a containing the impurity in the lowconcentration is located closer to the channel region, as compared withthe second and third SiGe layers; therefore, diffusion of boron from theSiGe layer due to a heat treatment is restrained, and the short channeleffect is prevented from being produced. Besides, in order to securelyprevent the short channel effect, the film thickness of the first SiGelayer 21a in the above-mentioned range is further preferably in therange of ten to 30 nm, within such a range as not to lower the carriermobility in the PMOSFET produced.

Incidentally, as has been described in the background of the inventionabove, there may be cases where an SiGe layer containing an impurity ina low concentration is formed on the surfaces on the recess regions, forconvenience of film formation, even in the case of directly forming theSiGe layer on the surfaces of the recess regions without changing thefilm forming conditions. The formation of the first SiGe layer 21a inthis embodiment, however, is different from such an incidental case.Specifically, the first SiGe layer 21a containing the impurity in thelow concentration is formed so as to have a predetermined filmthickness, by positively changing the film forming conditions.

Next, as shown in FIG. 1F, on the first SiGe layer 21a, the second SiGelayer 21b is epitaxially grown so as to contain the impurity with such aconcentration gradient that the impurity concentration therein variescontinuously from the impurity concentration in the first SiGe layer 21ato the impurity concentration in the third SiGe layer which will bedescribed later, along the direction from the first SiGe layer 21a sidetoward the surface thereof. Here, in view of that the boronconcentration in the first SiGe layer 21a is in the range of 1×10¹⁸ to1×10¹⁹ cm⁻³ and that the boron concentration in the third SiGe layer isin the range of 1×10¹⁹ to 5×10²⁰ cm⁻³, the second SiGe layer 21b is soformed as to contain boron with such a concentration gradient that theboron concentration therein varies continuously from the range of 1×10¹⁸to 1×10¹⁹ cm⁻³ to the range of 1×10¹⁹ to 5×10²⁰ cm⁻³, along thedirection from the first SiGe layer 21a side toward the surface thereof.The film thickness of the second SiGe layer 21b is one to 20 nm.

As for the film forming conditions for the second SiGe layer 21b, thesame film-forming gases as those in the case of the first SiGe layer 21aare used. Of the film-forming gases, DCS, GeH₄, and HCl are used at gasflow rates of DCS/GeH₄/HCl=ten to 100/ten to 100/ten to 100 (ml/min).Besides, the gas flow rate of B₂H₆ diluted by H₂ to 100 ppm is variedcontinuously from a value of one to 50 ml/min to a value of 50 to 300ml/min. In addition, the treating temperature is set in the range of 650to 750° C., and the treating pressure is in the range of 1.3 to 13.3kPa.

Here, the configuration in which the second SiGe layer 21b as above isinterposed between the first SiGe layer 21a being the lowest of thethree SiGe layers in impurity concentration and the third SiGe layerbeing the highest of the three SiGe layers in impurity concentrationmoderates the trouble in film formation due to the difference inimpurity concentration between the first SiGe layer 21a and the thirdSiGe layer. Therefore, the second SiGe layer 21b may not necessarily beprovided in the case where the difference in impurity concentrationbetween the first SiGe layer 21a and the third SiGe layer is small. Inaddition, while the second SiGe layer 21b is here formed so as tocontain the impurity in such a concentration gradient that the impurityconcentration therein varies continuously along the direction from theside of the first SiGe layer 21a toward the side of the third SiGelayer, the concentration variation may be stepwise. In that case, theB₂H₆ gas flow rate is changed stepwise.

Next, as shown in FIG. 1G, on the second SiGe layer 21b, the third SiGelayer 21c is formed so as to contain the impurity in the highestconcentration among the three SiGe layers. Here, the third SiGe layer21c is epitaxially grown to a film thickness of 50 to 100 nm so as tohave a boron concentration of 1×10¹⁹ to 5×10²⁰ cm⁻³.

As for the film forming conditions for the third SiGe layer 21c, thesame film-forming gases as those in the cases of the first SiGe layer21a and the second SiGe layer 21b are used at gas flow rates ofDCS/GeH₄/HCl/B₂H₆=ten to 100/ten to 100/ten to 100/50 to 300 (ml/min), atreating temperature of 650 to 750° C., and a treating pressure of 1.3to 13.3 kPa.

As a result, the SiGe layer 21 composed of the first SiGe layer 21a, thesecond SiGe layer band the third SiGe layer 21c which are sequentiallylayered in a stacked state is formed on the surfaces of the recessregions 16. Since the recess regions 16 are formed to be about 80 nmdeep, the recess regions 16 are filled sequentially with the first SiGelayer 21a, the second SiGe layer 21b and the third SiGe layer 21c, andthe third SiGe layer 21c is in the state of being protuberant upwardfrom the surface level of the silicon substrate 11. In addition, theSiGe layer 21 contains boron as an impurity with such a concentrationgradient that the impurity concentration therein increases along thedirection from the side of the silicon substrate 11 toward the surfacethereof.

The SiGe layers 21 form the source/drain regions of the PMOSFETmanufactured by the manufacturing method according to this embodiment,and the region of the silicon substrate 11 beneath the gate electrode 13located between the SiGe layers 21 becomes the channel region 18 of thePMOSFET.

The subsequent steps are carried out in the same manner as in the usualPMOSFET manufacturing method. For example, the face side of the SiGelayer 21 may be silicided to form a silicide layer. In this case, sincethe first SiGe layers 21a located close to the channel region 18 containthe impurity in the low concentration as above-mentioned, diffusion A ofthe impurity is restrained even when a heat treatment is conducted afterthe formation of the SiGe layer 21, and, therefore, the short channeleffect is prevented from being generated.

In this manner, a PMOSFET in which the channel region 18 is strained bythe stress (compressive stress) imposed on the channel region 18 by theSiGe layers 21 is manufactured.

According to the method of manufacturing a semiconductor device and thesemiconductor device as above-described, the SiGe layer 21 isepitaxially grown so as to contain the impurity with such aconcentration gradient that the impurity concentration therein increasesalong the direction from the side of the silicon substrate 11 toward thesurface thereof, so that the diffusion A of the impurity from the SiGelayer 21 due to a heat treatment is restrained, and the short channeleffect is prevented from being generated. Particularly, according tothis embodiment, the SiGe layer 21 is composed of the three SiGe layers,and the first SiGe layer 21a close to the channel region 18 is formed soas to contain the impurity in a lower concentration as compared with theother SiGe layers, so that the short channel effect can be securelyprevented from being produced. In addition, since it is unnecessary toenlarge the distance between the SiGe layer 21 and the region beneaththe gate electrode, a sufficient carrier mobility can be obtained.Therefore, transistor characteristics can be enhanced.

Furthermore, according to the method of manufacturing a semiconductordevice in this embodiment, the SiGe layer 21 having the impurityconcentration gradient can be formed by a series of operations in whichonly the film forming conditions are changed, without changing the kindsof the film-forming gases, which is excellent on a productivity basis.

Incidentally, while an example in which boron is contained as animpurity in the SiGe layer forming the source/drain regions of thePMOSFET has been described in the first embodiment above, otherimpurities than boron may be used, for example, gallium (Ga) or indium(In). For example, in the case of using Ga as the impurity,triethylgallium (Ga(C₂H₅)₃) or trimethylgallium (Ga(CH₃)₃) is used as afilm-forming gas, in place of B₂H₆ used in the first embodiment above.Similarly, in the case of using In as the impurity, triethylindium(In(C₂H₅)₃) or trimethylindium (In(CH₃)₃) is used, in place of B₂H₆, asa film-forming gas.

Second Embodiment

While the method of manufacturing a PMOSFET has been taken as an examplein the description of the first embodiment above, in this embodiment amethod of manufacturing an NMOSFET is taken as an example anddescription thereof will be made referring to FIGS. 2A to 2C.Incidentally, the steps up to the step of digging down the surface of asilicon substrate 11 are carried out in the same manner as the stepsdescribed referring to FIGS. 1A to 1D above.

In the case of manufacturing an NMOSFET, first, as shown in FIG. 2A, asilicon-carbon (SiC) layer (mixed crystal layer) composed of silicon(Si) and atoms (C) smaller in lattice constant than silicon andcontaining, for example, arsenic (As) as an impurity is epitaxiallygrown on the surfaces of recessed regions 16, i.e., on the surfaces ofthe dug-down portions of the silicon substrate 11.

In this case, also, the SiC layer is epitaxially grown so as to containAs with such a concentration gradient that the As concentration thereinincreases along, the direction from the side of the silicon substrate 11toward the surface thereof. Here, like in the first embodiment, the SiClayer is composed of a first SiC layer (first layer), a second SiC layer(second layer) and a third SiC layer (third layer) which aresequentially layered in a stacked state.

Specifically, on the surfaces of the dug-down portions of the siliconsubstrate 11, the first SiC layer 22a is formed so as to be the lowestof the three SiC layer in impurity concentration. Here, the first SiClayer 22a is formed in a film thickness of one to 30 nm so as to have anAs concentration of 1×10¹⁸ to 1×10¹⁹ cm⁻³.

As for the film forming conditions for the first SiC layer 22a, DCS,monomethylsilane (SiH₃CH₃) diluted with hydrogen (H₂) to one vol %, HCl,and arsenic hydride (AsH₃) diluted with hydrogen to one vol % are usedas film-forming gases, at gas flow rates of DCS/SiH₃CH₃/HCl/AsH₃=ten to100/one to 50/ten to 100/one to 25 (ml/min), a treating temperature of650 to 750° C., and a treating pressure of 1.3 to 13.3 kPa.

Here, as will be described later, the fist SiC layer 22a containing theimpurity in the low concentration is disposed to be the closest of thethree SiC layers to the channel region, so that diffusion of As from theSiC layer due to a heat treatment is restrained, and the short channeleffect is prevented from being produced. Besides, in order to securelyprevent the short channel effect, the film thickness of the first SiClayer 22a in the above-mentioned range is further preferably in therange of ten to 30 nm, within such a range as not to lower the carriermobility in the NMOSFET produced.

Next, as shown in FIG. 2B, on the first SiC layer 22a, the second SiClayer 22b is formed so as to contain the impurity with such aconcentration gradient that the impurity concentration therein variescontinuously from the impurity concentration in the first SiC layer 22ato the impurity concentration in the third SiC layer, along thedirection from the side of the first SiC layer 22a toward the surfacethereof. Here, in view of that the As concentration in the first SiClayer 22a is in the range of 1×1¹⁸ to 1×10¹⁹ cm⁻³ and that the Asconcentration in the third SiC layer is in the range of 1×10¹⁹ to 5×10²⁰cm⁻³ as will be described later, the second SiC layer 22b is so formedas to contain As with a concentration gradient such that the Asconcentration therein increases continuously from a value in the rangeof 1×10¹⁸ to 1×10¹⁹ cm⁻³ to a value in the range of 1×10¹⁹ to 5×10²⁰cm⁻³. The film thickness of the second SiC layer 22b is in the range ofone to 20 nm.

As for the film forming conditions for the second SiC layer 22b, thesame film-forming gases as in the case of the first SiC layer 22a aboveare used. Like in the case of the first SiC layer 22a, the gas flowrates of DCS, SiH₃CH₃ and HCl are set as DCS/SiH₃CH₃/HCl=ten to 100/oneto 50/ten to 100 (ml/min). On the other hand, the gas flow rate of AsH₃diluted with H₂ to one vol % is varied continuously from a value in therange of one to 25 ml/min to a value in the range of 25 to 50 ml/min.Besides, the treating temperature is set in the range of 650 to 750° C.,and the treating pressure in the range of 1.3 to 13.3 kPa.

Here, the configuration in which the second SiC layer 22b as above isinterposed between the first SiC layer 22a being the lowest of the threeSiC layers in impurity concentration and the third SiC layer being thehighest of the three SiC layers in impurity concentration moderates thetrouble in film formation due to the difference in impurityconcentration between the first SiC layer 22a and the third SiC layer.Therefore, the second SiC layer 22b may not necessarily be provided inthe case where the difference in impurity concentration between thefirst SiC layer 22a and the third SiC layer is small. In addition, whilethe second SiC layer 22b is here formed so as to contain the impurity insuch a concentration gradient that the impurity concentration thereinvaries continuously along the direction from the side of the first SiClayer 22a toward the side of the third SiC layer, the concentrationvariation may be stepwise. In that case, the AsH₃ gas flow rate ischanged stepwise.

Next, as shown in FIG. 2C, on the second SiC layer 22b, the third SiClayer 22c is formed so as to contain the impurity in the highestconcentration among the three SiC layers. Here, the third SiC layer 22cis formed in a film thickness of 50 to 100 nm so as to have an Asconcentration of 1×10¹⁹ to 5×10²⁰ cm⁻³.

As for the film forming conditions for the third SiC layer 22c, the samefilm-forming gases as those in the cases of the first SiC layer 22a andthe second SiC layer 22b are used at gas flow rates ofDCS/SiH₃CH₃/HCl/AsH₃=ten to 100/one to 50/ten to 100/25 to 50 (ml/min),a treating temperature of 650 to 750° C., and a treating pressure of 1.3to 13.3 kPa.

As a result, the SiC layer 22 composed of the first SiC layer 22a, thesecond SiC layer 22b and the third SiC layer 22c which are sequentiallylayered in a stacked state is formed on the surfaces of the recessregions 16. Since the recess regions 16 are formed to be about 80 nmdeep, the recess regions 16 are filled sequentially with the first SiClayer 22a, the second SiC layer 22b and the third SiC layer 22c, and thethird SiC layer 22c is in the state of being protuberant upward from thesurface level of the silicon substrate 11. In addition, the SiC layer 22contains As as an impurity with such a concentration gradient that theimpurity concentration therein increases along the direction from theside of the silicon substrate 11 toward the surface thereof.

The SiC layers 22 form the source/drain regions of the NMOSFETmanufactured by the manufacturing method according to this embodiment,and the region of the silicon substrate 11 beneath the gate electrode 13located between the SiC layers 22 becomes the channel region 18 of theNMOSFET.

The subsequent steps are carried out in the same manner as in the usualNMOSFET manufacturing method. For example, the face side of the SiClayer 22 may be silicided to form a silicide layer. In this case, sincethe first SiC layers 22a located close to the channel region 18 containthe impurity in the low concentration as above-mentioned, diffusion A ofthe impurity is restrained even when a heat treatment is conducted afterthe formation of the SiC layer 22, and, therefore, the short channeleffect is prevented from being generated.

In this manner, an NMOSFET in which the channel region 18 is strained bythe stress (compressive stress) imposed on the channel region 18 by theSiC layers 22 is manufactured.

According to the method of manufacturing a semiconductor device and thesemiconductor device as above-described, the SiC layer 22 is epitaxiallygrown so as to contain the impurity with such a concentration gradientthat the impurity concentration therein increases along the directionfrom the side of the silicon substrate 11 toward the surface thereof, sothat the diffusion A of the impurity from the SiC layer 22 due to a heattreatment is restrained, and the short channel effect is prevented frombeing generated. Particularly, according to this embodiment, the SiClayer 22 is composed of the three SiC layers, and the first SiC layer22a close to the channel region 18 is formed so as to contain theimpurity in a lower concentration as compared with the other SiC layers,so that the short channel effect can be securely prevented from beingproduced. In addition, since it is unnecessary to enlarge the distancebetween the SiC layer 22 and the region beneath the gate electrode, asufficient carrier mobility can be obtained. Therefore, transistorcharacteristics can be enhanced.

MODIFIED EXAMPLE 1

While an example in which As is contained as an impurity in the SiClayer for forming the source/drain regions of the NMOSFET has beendescribed in the second embodiment above, phosphorus (P) may be used, inplace of As, as the impurity.

In this case, also, the first SiC layer 22a is formed in a filmthickness of one to 30 nm so as to contain P as the impurity in aconcentration in the range of 1×10¹⁸ to 1×10¹⁹ cm⁻³.

As for the film forming conditions for the first SiC layer 22a, DCS,SiH₃CH₃ diluted with hydrogen (H₂) to one vol %, HCl, and phosphorushydride (PH₃) diluted with H₂ to 50 ppm are used as film-forming gases,at gas flow rates of DCS/SiH₃CH₃/HCl/PH₃=ten to 100/one to 50/ten to100/one to 150 (ml/min), a treating temperature of 650 to 750° C., and atreating pressure of 1.3 to 13.3 kPa.

Next, on the first SiC layer 22a, a second SiC layer 22b is formed in afilm thickness of one to 20 nm so as to contain P as an impurity withsuch a concentration gradient that the impurity concentration thereinincreases from a value in the range of 1×10¹⁸ to 1×10¹⁹ cm⁻³ to a valuein the range of 1×10¹⁹ to 5×10²⁰ cm⁻³, along the direction from the sideof the first SiC layer 22a toward the surface thereof.

As for the film forming conditions for the second SiC layer 22b, thesame film-forming gases as in the case of the first SiC layer 22a aboveare used. The gas flow rates of DCS, SiH₃CH₃ and HCl are set asDCS/SiH₃CH₃/HCl=ten to 100/one to 50/ten to 100 (ml/min). On the otherhand, the gas flow rate of PH₃ diluted with H₂ to 50 ppm variedcontinuously or stepwise from a value in the range of one to 150 ml/minto a value in the range of 150 to 300 ml/min. Besides, the treatingtemperature is set in the range of 650 to 750° C., and the treatingpressure in the range of 1.3 to 13.3 kPa.

Next, on the second SiC layer 22b, the third SiC layer 22c is formed ina film thickness of 50 to 100 nm so as to contain P as an impurity in aconcentration in the range of 1×10¹⁹ to 5×10²⁰ cm⁻³.

As for the film forming conditions for the third SiC layer 22c, the samefilm-forming gases as those in the cases of the first SiC layer 22a andthe second SiC layer 22b are used at gas flow rates ofDCS/SiH₃CH₃/HCl/PH₃=ten to 100/one to 50/ten to 100/150 to 300 (ml/min),a treating temperature of 650 to 750° C., and a treating pressure of 1.3to 13.3 kPa.

By the method of manufacturing an NMOSFET and the NMOSFET asjust-described, also, the same effects as in the second embodiment abovecan be displayed.

Incidentally, in the first and second embodiments and the modifiedexample 1 above, descriptions have been made of examples in which themixed crystal layer composed of a SiGe layer or SiC layer is configuredof the first layer, the second layer and the third layer sequentiallylayered in a stacked state. The first layer and the third layer are eachformed to maintain an impurity concentration in a predetermined range,and the second layer is so formed as to have such a concentrationgradient that the impurity concentration therein increases continuouslyfrom the first layer side toward the third layer side. However, such aconfiguration is non-limitative of the present invention. For example,the mixed crystal layer may be composed of a plurality of layerscontaining an impurity with such a concentration gradient that theimpurity concentration increases stepwise along the direction from thesilicon substrate side toward the surface thereof. Otherwise, the mixedcrystal layer may be composed of a single layer containing an impuritywith such a concentration gradient that the impurity concentrationincreases continuously along the direction from the silicon substrateside toward the surface thereof. It should be noted here, however, thatthe portion, near the channel region, of the mixed crystal layerpreferably has a region kept at a low impurity concentration in a filmthickness of ten to 30 nm.

In addition, while a method of manufacturing a semiconductor device bywhich a PMOSFET or NMOSFET is produced has been described in each of theabove embodiments, the present invention is applicable also to the caseof producing a CMOS (Complementary Metal Oxide Semiconductor) FET inwhich both a PMOSFET and an NMOSFET are mounted.

It should be understood by those skilled in the art that variousmodifications, combinations, sub-combinations and alterations may occurdepending on design requirements and other factors insofar as they arewithin the scope of the appended claims or the equivalents thereof.

What is claimed is:
 1. A method of manufacturing a semiconductor device,comprising: the first step of forming a gate electrode over a siliconsubstrate, with a gate insulating film; the second step of digging downa surface layer of said silicon substrate by etching conducted with saidgate electrode as a mask; and the third step of epitaxially growing, onthe surface of said dug-down portion of said silicon substrate, a mixedcrystal layer including silicon and atoms different in lattice constantfrom silicon so that said mixed crystal layer contains an impurity withsuch a concentration gradient that the impurity concentration increasesalong the direction from said silicon substrate side toward the surfaceof said mixed crystal layer, wherein, said third step includesepitaxially growing said mixed crystal layer so that said mixed crystallayer contains the impurity with said concentration gradient such thatsaid impurity concentration increases stepwise along the direction fromsaid silicon substrate side toward the surface of said mixed crystallayer.
 2. The method of manufacturing a semiconductor device as setforth in claim 1, wherein said semiconductor device is a p-type fieldeffect transistor, and said third step includes epitaxially growing, onthe surface of said silicon substrate, said mixed crystal layerincluding silicon and germanium so that said mixed crystal layercontains the p-type impurity with said concentration gradient.
 3. Themethod of manufacturing a semiconductor device as set forth in claim 1,wherein said semiconductor device is an n-type field effect transistor,and said third step includes epitaxially growing, on the surface of saidsilicon substrate, said mixed crystal layer including silicon and carbonso that said mixed crystal layer contains the n-type impurity with saidconcentration gradient.
 4. The method of manufacturing a semiconductordevice as set forth in claim 1, wherein said third step includesepitaxially growing said mixed crystal layer so that said mixed crystallayer contains the impurity with said concentration gradient such thatsaid impurity concentration increases continuously along the directionfrom said silicon substrate side toward the surface of said mixedcrystal layer.
 5. The method of manufacturing a semiconductor device asset forth in claim 1, wherein said mixed crystal layer includes a firstlayer, a second layer, and a third layer sequentially layered in astacked state, and said third step includes the steps of: forming saidfirst layer on the surface of said dug-down portion of said siliconsubstrate so that said first layer contains said impurity in the lowestconcentration among said three layers; forming said second layer on saidfirst layer so that said second layer contains said impurity with such aconcentration gradient that the impurity concentration in said secondlayer increases from the impurity concentration in said first layer tothe impurity concentration in said third layer; and forming said thirdlayer on said second layer so that said third layer contains saidimpurity in the highest concentration among said three layers.
 6. Amethod of manufacturing a semiconductor device, comprising: a first stepof forming a mask, wherein the mask comprises: a first gate electrodeover a silicon substrate, a first side wall on a lateral side of thefirst gate electrode, a second gate electrode over the siliconsubstrate, and a second side wall on a lateral side of the second gateelectrode; a second step of digging down by etching, with the mask, asurface of the silicon substrate in a manner that forms a dug-downportion of the silicon substrate; and a third step of epitaxiallygrowing a mixed crystal layer that includes: silicon and atoms differentin lattice constant from silicon so that the mixed crystal layercontains an impurity with such a concentration gradient that aconcentration of the impurity increases stepwise along a first directionfrom the silicon substrate toward a surface of the mixed crystal layer,wherein the mixed crystal layer comprises: a first layer that is grownon a surface of the dug-down portion in a manner that causes the firstlayer to extend from the first side wall to the second side wall, and asecond layer that is grown on the first layer in a manner that causesthe second layer to extend from the first side wall to the second sidewall, a third layer that is grown on the second layer, wherein aconcentration of the impurity in the first layer is lower than aconcentration of the impurity in the second layer, wherein the thirdlayer is a topmost layer of the mixed crystal layer, protrudes in thefirst direction from a surface level of the silicon substrate, and has afilm thickness of at least 50 nm.
 7. The method of manufacturing asemiconductor device as set forth in claim 6, wherein the concentrationof the impurity in the second layer is lower than a concentration of theimpurity in the third layer.
 8. The method of manufacturing asemiconductor device as set forth in claim 7, wherein the second layeris between the first layer and the third layer.
 9. The method ofmanufacturing a semiconductor device as set forth in claim 7, whereinthe third concentration is 1×10¹⁹ to 5×10²⁰ cm⁻³.
 10. The method ofmanufacturing a semiconductor device as set forth in claim 7, whereinthe first layer and the second layer and the third layer are formed by asame film-forming gases with a same flow rate.
 11. The method ofmanufacturing a semiconductor device as set forth in claim 7, whereinthe film thickness of the third layer is 50 to 100 nm.
 12. The method ofmanufacturing a semiconductor device as set forth in claim 6, whereinthe mask exposes the surface of the silicon substrate in the secondstep.
 13. The method of manufacturing a semiconductor device as setforth in claim 6, wherein etching in the second step is isotropicetching.
 14. The method of manufacturing a semiconductor device as setforth in claim 6, wherein the impurity is introduced in the third stepusing in-situ doping.
 15. The method of manufacturing a semiconductordevice as set forth in claim 6, wherein the second concentration variescontinuously from the first concentration to the third concentration.16. The method of manufacturing a semiconductor device as set forth inclaim 6, wherein the first concentration is 1×10¹⁸ to 1×10¹⁹ cm⁻³. 17.The method of manufacturing a semiconductor device as set forth claim 6,wherein the second concentration has a concentration gradient increasingfrom (1) a range of 1×10¹⁸ to 1×10¹⁹ cm⁻³ to (2) a range of 1×10¹⁹ to5×10²⁰ cm⁻³.
 18. The method of manufacturing a semiconductor device asset forth in claim 6, wherein the mixed crystal layer comprises animpurity selected from a group of consisting of boron, arsenic,phosphorus and a combination thereof.
 19. The method of manufacturing asemiconductor device as set forth claim 6, wherein the semiconductordevice is a p-type field effect transistor.
 20. The method ofmanufacturing a semiconductor device as set forth in claim 6, whereinthe impurity is a p-type impurity.
 21. The method of manufacturing asemiconductor device as set forth in claim 20, wherein the atomsdifferent in lattice constant from silicon is germanium.
 22. The methodof manufacturing a semiconductor device as set forth in claim 6, whereinthe semiconductor device is an n-type field effect transistor.
 23. Themethod of manufacturing a semiconductor device as set forth in claim 6,wherein the impurity is an n-type impurity.
 24. The method ofmanufacturing a semiconductor device as set forth in claim 23, whereinthe atoms different in lattice constant from silicon is carbon.
 25. Themethod of manufacturing a semiconductor device as set forth in claim 6,wherein the film thickness of the first layer is 10 to 30 nm.
 26. Themethod of manufacturing a semiconductor device as set forth in claim 6,wherein the film thickness of the second layer is 1 to 20 nm.
 27. Themethod of manufacturing a semiconductor device as set forth in claim 6,wherein a depth of the dug-down portion is about 80 nm.